• The basic idea is a programming language to describe the hardware
• The module begins withmodulekeyword and finishes with theendmodule.
• The internal signals are named with thewire.
• Comments follow//
• Theinputandoutputare ports. These are placed at the beginning of module definition.
• Each statement ends with the semicolon, except theendmodule.
• Design entry by using both behavior and structure
• Simulation modelling
• Testing
• This is a standard language
• Register –It retains the last value assigned to it. Used to represent the storage elements.
• „wire? equivalent; when there are multiple present for drivers driving them, the outputs of the drivers are shorted together.
• Arithmetic operators - *, /, +, -, %
• Logical operators - ! logical negation && logical AND | | logical OR
• Relational operators >, <, >=, <=, ==, !=
• Bitwise operators ~, &, |, ^, ~^
• Reduction operators (operate on all bits within the word) &, ~&, |, ~|, ^, ~^
• accepts a single word operand and generates a single bit as output
• Shift operators >>, <<
• Concatenation { }
• Replication { n { } }
• Conditional ? :

The Basic Structure

modulemodule_name(list_of_ports);

input/outputdeclarations;

localnetdeclarations;

parallelstatements;

endmodule

SimpleANDcircuitforHDL

module simpleand (f, x, y);

input x, y;

output f;

assign f = x & y;

endmodule

Simple circuit diagram

SimpleHDL

module smpl_circuit(A,B,C,x,y);

inputA,B,C;outputx,y;wiree;

andg1(e,A,B);